The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to improvements in chemical mechanical polishing processes and components.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a patterned stop layer, and planarizing the filler layer until the stop layer is exposed. For example, a conductive filler layer may be deposited on a patterned insulative stop layer to fill the trenches or holes in the stop layer. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a Astandard@ pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished (lacks small-scale roughness) and flat (lacks large-scale topography). The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad. The polishing rate sets the time needed to polish a layer. Because inadequate flatness and finish can create defective substrates, the selection of a polishing pad and slurry combination is usually dictated by the required finish and flatness. Given these constraints, the polishing time needed to achieve the required finish and flatness sets the maximum throughput of the CMP apparatus.
A recurring problem in CMP is so-called Adishing@ in the substrate surface. Specifically, when the stop layer is exposed, the portion of the filler layer between the raised areas of the patterned stop layer can be overpolished, creating concave depressions in the substrate surface. Dishing can render the substrate unsuitable for integrated circuit fabrication, lowering process yield.
In one aspect, the invention is directed to a method of chemical mechanical polishing a substrate having a filler layer disposed on a stop layer. In the method, the substrate is chemical mechanical polished with a single layer hard polishing pad and a first slurry until the stop layer is at least partially exposed. Then the substrate is chemical mechanical polished with a soft polishing pad and a second slurry which has a lower selectivity than the first slurry until the stop layer is substantially exposed.
Implementations of the invention may include one or more of the following features. A pressure equal or less than about 5 psi, e.g., less than 2.9 psi, may be applied to said substrate during polishing. The first slurry may have a selectivity greater than about 20:1, and the second slurry may have a selectivity less than about 6:1. The system may sense when the stop layer is at least partially exposed and when the stop layer is substantially exposed with an endpoint detector. The single layer hard polishing pad may comprise polyurethane or abrasive particles embedded in a matrix. The filler layer may be a metal and the stop layer may be a dielectric material. Alternatively, the filler layer may be a first dielectric and the stop layer is a second dielectric material.
In another aspect, the invention is directed to a method of chemical mechanical polishing a substrate having a filler layer disposed on a stop layer. The substrate is chemical mechanical polished with a single layer hard polishing pad and a first slurry until the stop layer is at substantially entirely exposed. Then the substrate is chemical mechanical polished with a soft polishing pad and a second slurry which has a lower selectivity than the first slurry.
In yet another aspect, the invention is directed to a method of chemical mechanical polishing a substrate having an upper layer disposed over a lower layer. In the method, the substrate is chemical mechanical polished with a stacked polishing pad, the stacked polishing pad having at least a first layer disposed on top of a second layer, the first layer being harder than the second layer. Then the substrate is chemical mechanical polished with a single layer hard polishing pad. Then the substrate is chemical mechanical polished with a third polishing pad. The third polishing pad is softer than the single layer hard pad.
Implementations of the invention may include one or more of the following features. Polishing with the stacked polishing pad may stop when the lower layer is partially exposed. Polishing with the single layer hard polishing pad may stop when the lower layer is substantially entirely exposed. Alternatively, polishing with the stacked polishing pad may ends when the lower layer is substantially entirely exposed. Polishing with the stacked polishing pad may be performed with a first slurry, polishing with the single layer hard polishing pad may be performed with a second slurry, and the first slurry may have a higher selectivity than a second slurry. Polishing with the stacked polishing pad and the single layer polishing pad may be performed with a first slurry, polishing with the soft polishing pad may be performed with a second slurry, and the first slurry may have a higher selectivity than a second slurry. The single layer polishing pad may includes abrasive particles.
Potential advantages that may be seen in implementations of the invention may include zero or more of the following. Dishing in the substrate surface may be reduced or eliminated, thereby increasing process yield. Consistently low within wafer non-uniformity may be achieved. Erosion of the stop layer may be reduced. A thinner filler layer may be used, thereby decreasing the polishing time and increasing the throughput of the CMP apparatus. The substrate may be buffed for a longer period of time, thereby improving the substrate finish. All these approaches are also applicable to STI CMP in an IC production fab for different devices (0.25 {grave over (l)}m and beyond) ranging from microprocessor to memory to analog devices having different pattern densities.
Other features and advantages will be apparent from the following description, including the drawings and claims.